This invention relates to semiconductor memory devices and methods of manufacture, and more particularly to an improved method for making a one-transistor dynamic read/write memory device of the N-channel silicon gate type.
Dynamic read/write memory cells made by the single-level or double-level polysilicon N-channel self-aligned processes commonly used in the industry are shown in U.S. Pat. No. 4,055,444 as well as in pending U.S. Patent applications Ser. No. 648,594, filed Jan. 12, 1976 and Ser. No. 722,841, filed Sept. 13, 1976, by C-K Kuo, all assigned to Texas Instruments; these processes are also known in Electronics: Feb. 19, 1976, pp. 116-121; May 13, 1976, pp 81-86; and Sept. 28, 1978, pp. 109-116.
In typical dynamic RAM cell arrays, the source/drain regions and "bit" lines (Y or column input/output lines) are usually formed of elongated N+ silicon regions. As the cell sizes and device geometries have been "scaled" to produce arrays of higher density, it has become the usual practice to form these N+ regions by an arsenic implant instead of by a phosphorus diffusion as had been previously employed. At the point in the process where the implant is performed polysilicon layers are in place for the transistor gates and capacitor gates. These are floating and are separated from the silicon surface by a thin gate oxide, perhaps 400 .ANG.. One of the most common failure modes in high density dynamic RAMS is that of electrical shorting between the polysilicon and substrate through this gate oxide. At high implant dosages and/or currents as needed for source/drain implants, a static charge builds up on the polysilicon to levels which can break down the gate oxide. This failure mode is reduced by use of thicker gate oxide, or of course by reducing the plant dosage, but these solutions are limited by bar size, N+ resistivity, access time, and other constraints.
It is the principal object of this invention to provide an improved method of making dynamic read/write memory devices of the "scaled" type having thin gate oxide and thin implanted source/drain regions. Another object is to provide a high yield manufacturing method for a dynamic memory cell array of reduced cell size. An additional object is to provide a dense array of DRAM memory cells, made by an improved method which provides a reduction in failures due to shorting through thin oxide.